VHDL code for 2x1 Multiplexer

library ieee;
use ieee.std_logic_1164.all;

entity bejoy_2x1 is
port(d0,d1,s:in std_logic;

z:out std_logic;
z1,z2: inout std_logic);
end bejoy_2x1;

architecture arc of bejoy_2x1 is
begin
z1 <= d0 and (not s);
z2 <= (d1 and s);
z <= z1 or z2;
end arc;