library ieee;
use ieee.std_logic_1164.all;
entity bejoy_ep is
port(x,y,z:in std_logic;
p:out std_logic);
end bejoy_ep;
architecture a of bejoy_ep is
begin
p<=((x xor y) xnor z);
end a;
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Thursday, April 12, 2012
VHDL code for Even Parity Generator
Thursday, April 12, 2012
Electronics, VHDL