library ieee;
use ieee.std_logic_1164.all;
entity bejoy_tff is
port(t,clk:in std_logic;q,q1,z:inout std_logic);
end bejoy_tff;
architecture arc of bejoy_tff is
begin
process(clk)
begin
if clk='1' then
z<=((t and (not q)) or ((not t) and q));
q<=z after 5ns;
q1<=not z after 5ns;
end if;
end process;
end arc;
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Tuesday, April 10, 2012
VHDL code for T Flip Flop
Tuesday, April 10, 2012
Electronics, VHDL