library ieee;
use ieee.std_logic_1164.all;
entity bejoy_op is
port(x,y,z:in std_logic;
p:out std_logic);
end bejoy_op;
architecture a of bejoy_op is
begin
p<=((x xor y) xor z);
end a;
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Tuesday, April 10, 2012
VHDL code for Odd Parity Generator
Tuesday, April 10, 2012
Electronics, VHDL