VHDL code for 3x8 Decoder

library ieee;use ieee.std_logic_1164.all;entity bejoy_3x8 isport(a,b,c:in std_logic;d0,d1,d2,d3,d4,d5,d6,d7:out std_logic);end bejoy_3x8;architecture arc of bejoy_3x8 isbegind0<= (not a) and (not b) and (not c);d1<= (not a) and (not b) and c;d2<= (not a) and b and (not c);d3<= (not a) and b and c;d4<= a and (not b) and (not c);d5<= a and (not b) and c;d6<= a and b and (not c);d7<= a and b and c;end a...

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VIPRE Antivirus 2012 5.0.1135

VIPRE Antivirus 2012 - an easy and very effective anti-virus program that does not slow down your PC. Using next generation technology, VIPRE protects your computer from all types of malware threats including viruses, adware, spyware, worms, rootkits and other malicious software.VIPRE Antivirus 2012 - an easy and very effective anti-virus program that does not slow down your PC. Using next generation technology, VIPRE protects your computer from...

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VHDL code for JK Flip Flop

library ieee;use ieee.std_logic_1164.all;entity bejoy_jkff isport(j,k,clk:in std_logic;q,q1,z:inout std_logic);end bejoy_jkff;architecture arc of bejoy_jkff isbeginprocess(clk)beginif clk='1' thenz<=(j and (not q)) or ((not k) and q);q<=z after 5ns;q1<=not z after 5ns;end if;end process;end a...

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Kaspersky Anti-Virus 2013 13.0.0.3011 Technical Preview

Kaspersky Anti-Virus 2013 – the backbone of your PC’s security system, offering protection from a range of IT threats. Kaspersky Anti-Virus 2013 provides the basic tools needed to protect your PC.Kaspersky Internet Security 2013 – the all-in-one security solution that offers a worry-free computing environment for you and your family. Kaspersky Internet Security 2013 has everything you need for a safe and secure Internet experience. Kaspersky Internet...

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VHDL code for Full Adder using structural style

library IEEE;use IEEE.std_logic_1164.all;entity bejoy_fa isport(In1,In2,c_in : in std_logic;sum, c_out : out std_logic);end bejoy_fa;architecture arc of bejoy_fa iscomponent half_adderport(a,b : in std_logic;sum, carry : out std_logic);end component;component or_2port(a,b : in std_logic;c : out std_logic);end component;signal s1, s2, s3 : std_logic;beginH1: half_adder port map(a=>In1, b=>In2, sum=>s1, carry=>s3);H2: half_adder port map(a=>s1, b=>c_in, sum=>sum, carry=>s2);O1: or_2 port map(a=> s2, b=>s3, c=>c_out);end...

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100 Watt Audio Power Amplifier

This is an exceptionally well designed amplifier, with a lot of power reserve, high fidelity, low distortion, good S/N ratio, high sensitivity, low consumption and full protection. Having all these almost ideal characteristics this amplifier is likely to become the basic building block of your future high fidelity system, or it can also become the element that will upgrade your existing system. How it Works The circuit works from a symmetrical ñ...

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VHDL code for Half Adder

library ieee;use ieee.std_logic_1164.all;entity bejoy_ha isport (a,b : in bit ;s,c : out bit);end bejoy_ha;architecture arc of bejoy_ha isbegins<= a xor b;c <= a and b;end a...

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50 watts transistor amplifier

The amplifier and speakers that can handle medium-power is designed to provide a strictly amateur. Accidental overloads can damage the speakers, it is not appropriate for small systems.What amp settings do not contain an element of the first connection wiring must be careful to work with.Characteristics of the transistor, the fan or heat sink is cooled enough to find out if you need to focus!Tech. parameters:Power: + - 28VPower: 50W / 4 ohmsInput...

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Fet Buffer for amplifiers

source: http://cappels.org/dproj/edfet/edfet.htmlThe EDFET drives like a FET, but with the bias stability of bipolar. Amps of output current can be controlled by milliamps of input current. The current gain is a design choice dictated by bandwidth. Two of things you have to consider when adding a power output stage to an op-amp circuit are the frequency response and the cross-over distortion in that stage.This is especially true with wide band amplifiers,...

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VHDL code for 1x2 Demultiplexer

library ieee;use ieee.std_logic_1164.all;entity bejoy_1x2 isport(d,s:in std_logic;z0,z1:out std_logic);end bejoy_1x2;architecture arc of bejoy_1x2 isbeginz0 <= d and (not s);z1 <= (d and s);end a...

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