library ieee;use ieee.std_logic_1164.all;entity bejoy_ep isport(x,y,z:in std_logic;p:out std_logic);end bejoy_ep;architecture a of bejoy_ep isbeginp<=((x xor y) xnor z);end...
Thursday, April 12, 2012
VHDL code for Half Subtractor
library ieee;use ieee.std_logic_1164.all;entity bejoy_hs isport (x,y,en : in bit ;d,b : out bit; y1: inout bit);end bejoy_hs;architecture arc of bejoy_hs isbeginprocess (en,y1)beginif en='1' thend<= x xor y;y1<= not (y);b <= x and y1;end if;end process;end a...
Wednesday, April 11, 2012
VHDL code for 4x1 Multiplexer using structural style
library IEEE;use IEEE.std_logic_1164.all;entity bejoy_4x1 isport(s1,s2,d00,d01,d10,d11 : in std_logic;z_out : out std_logic);end bejoy_4x1;architecture arc of bejoy_4x1 iscomponent muxport(sx1,sx2,d0,d1 : in std_logic;z : out std_logic);end component;component or_2port(a,b : in std_logic;c : out std_logic);end component;signal intr1, intr2, intr3, intr4 : std_logic;beginmux1 : mux port map(s1,s2,d00,d01,intr1);mux2 : mux port map(not s1,s2, d10,d11,intr2);o1 : or_2 port map(intr1, intr2, z_out);end arc;library ieee;use ieee.std_logic_1164.all;entity...
VHDL code for Basic Gates
AND Gatelibrary ieee;use ieee.std_logic_1164.all;entity and_gate isport (a,b : in std_logic ;c : out std_logic);end and_gate;architecture arc of and_gate isbeginc <= a and b; end arc; OR Gatelibrary ieee;use ieee.std_logic_1164.all;entity or_gate isport (a,b : in std_logic ;c : out std_logic);end or_gate;architecture arc of or_gate isbeginc <= a or b; end arc; NOT Gatelibrary ieee;use ieee.std_logic_1164.all;entity not_gate isport (a: in std_logic ;b : out std_logic);end not_gate;architecture arc of not_gate isbeginb <= not a; end arc;...
Tuesday, April 10, 2012
Master Slave JK Flip Flop
library ieee;use ieee.std_logic_1164.all;entity master_slave_jk isport(j,k,clk:in std_logic;q1,q1x,z1x:inout std_logic;q2,q2x,z2x: inout std_logic);end master_slave_jk;architecture arc of master_slave_jk isbeginprocess(clk)beginif clk='1' thenz1x<=(j and (not q2)) or ((not k)and q2);q1<=z1x after 5 ns;q1x<=not z1x after 5ns; else z2x<=(q1 and (not q2)) or ((not q1x)and q2);q2<=z2x after 5 ns;q2x<=not z2x after 5ns;end if;end process;end...
VHDL code for T Flip Flop
library ieee;use ieee.std_logic_1164.all;entity bejoy_tff isport(t,clk:in std_logic;q,q1,z:inout std_logic);end bejoy_tff;architecture arc of bejoy_tff isbeginprocess(clk)beginif clk='1' thenz<=((t and (not q)) or ((not t) and q));q<=z after 5ns;q1<=not z after 5ns;end if;end process;end a...
VHDL code for Odd Parity Generator
library ieee;use ieee.std_logic_1164.all;entity bejoy_op isport(x,y,z:in std_logic;p:out std_logic);end bejoy_op;architecture a of bejoy_op isbeginp<=((x xor y) xor z);end...
Monday, April 9, 2012
VHDL code for 3x8 Decoder
library ieee;use ieee.std_logic_1164.all;entity bejoy_3x8 isport(a,b,c:in std_logic;d0,d1,d2,d3,d4,d5,d6,d7:out std_logic);end bejoy_3x8;architecture arc of bejoy_3x8 isbegind0<= (not a) and (not b) and (not c);d1<= (not a) and (not b) and c;d2<= (not a) and b and (not c);d3<= (not a) and b and c;d4<= a and (not b) and (not c);d5<= a and (not b) and c;d6<= a and b and (not c);d7<= a and b and c;end a...
VHDL code for JK Flip Flop
library ieee;use ieee.std_logic_1164.all;entity bejoy_jkff isport(j,k,clk:in std_logic;q,q1,z:inout std_logic);end bejoy_jkff;architecture arc of bejoy_jkff isbeginprocess(clk)beginif clk='1' thenz<=(j and (not q)) or ((not k) and q);q<=z after 5ns;q1<=not z after 5ns;end if;end process;end a...
Sunday, April 8, 2012
VHDL code for Full Adder using structural style
library IEEE;use IEEE.std_logic_1164.all;entity bejoy_fa isport(In1,In2,c_in : in std_logic;sum, c_out : out std_logic);end bejoy_fa;architecture arc of bejoy_fa iscomponent half_adderport(a,b : in std_logic;sum, carry : out std_logic);end component;component or_2port(a,b : in std_logic;c : out std_logic);end component;signal s1, s2, s3 : std_logic;beginH1: half_adder port map(a=>In1, b=>In2, sum=>s1, carry=>s3);H2: half_adder port map(a=>s1, b=>c_in, sum=>sum, carry=>s2);O1: or_2 port map(a=> s2, b=>s3, c=>c_out);end...
100 Watt Audio Power Amplifier
This is an exceptionally well designed amplifier, with a lot of power reserve, high fidelity, low distortion, good S/N ratio, high sensitivity, low consumption and full protection. Having all these almost ideal characteristics this amplifier is likely to become the basic building block of your future high fidelity system, or it can also become the element that will upgrade your existing system. How it Works The circuit works from a symmetrical ñ...
VHDL code for Half Adder
library ieee;use ieee.std_logic_1164.all;entity bejoy_ha isport (a,b : in bit ;s,c : out bit);end bejoy_ha;architecture arc of bejoy_ha isbegins<= a xor b;c <= a and b;end a...
50 watts transistor amplifier
The amplifier and speakers that can handle medium-power is designed to provide a strictly amateur. Accidental overloads can damage the speakers, it is not appropriate for small systems.What amp settings do not contain an element of the first connection wiring must be careful to work with.Characteristics of the transistor, the fan or heat sink is cooled enough to find out if you need to focus!Tech. parameters:Power: + - 28VPower: 50W / 4 ohmsInput...
Saturday, April 7, 2012
Fet Buffer for amplifiers
source: http://cappels.org/dproj/edfet/edfet.htmlThe EDFET drives like a FET, but with the bias stability of bipolar. Amps of output current can be controlled by milliamps of input current. The current gain is a design choice dictated by bandwidth. Two of things you have to consider when adding a power output stage to an op-amp circuit are the frequency response and the cross-over distortion in that stage.This is especially true with wide band amplifiers,...
VHDL code for 1x2 Demultiplexer
library ieee;use ieee.std_logic_1164.all;entity bejoy_1x2 isport(d,s:in std_logic;z0,z1:out std_logic);end bejoy_1x2;architecture arc of bejoy_1x2 isbeginz0 <= d and (not s);z1 <= (d and s);end a...
Design Buffers: Improved unity-gain follower delivers fast, stable response
Robert A Pease, National Semiconductor Corp -- EDN, June 27, 2011Heavy load capacitance can cause the output of a unity-gain follower—an operational amplifier with direct feedback to the inverting input (Fig 1)—to ring and oscillate. The LM110 follower, for example, normally drives a 50-pF load without problems, but it does not drive 500 pF stably—high capacitance significantly modifies the open-loop output impedance, reducing the phase margin to...
VHDL code for Full Subtractor
library ieee;use ieee.std_logic_1164.all;entity bejoy_fs isport(x,y,bi: in bit; b2,do,bo: out bit; d,b: inout bit);end bejoy_fs;architecture arc of bejoy_fs isbegind<=x xor y;b<=x and (not y);do<=bi xor d;b2<=bi and (not b);end a...
VHDL code for 4 bit Gray to Binary converter
library ieee;use ieee.std_logic_1164.all;entity bejoy_g2b isport(g:in std_logic_vector(3 downto 0);b:inout std_logic_vector(3 downto 0));end bejoy_g2b;architecture a of bejoy_g2b isbeginb(3)<=g(3);b(2)<=b(3) xor g(2);b(1)<=b(2) xor g(1);b(0)<=b(1) xor g(0);end...
Friday, April 6, 2012
VHDL code for 4 bit Binary to Gray code converter
library ieee;use ieee.std_logic_1164.all;entity bejoy_b2g isport(b:in std_logic_vector(3 downto 0);g:out std_logic_vector(3 downto 0));end bejoy_b2g;architecture a of bejoy_b2g isbeging(3)<=b(3);g(2)<=b(3) xor b(2);g(1)<=b(2) xor b(1);g(0)<=b(1) xor b(0);end...
VHDL code for SR Flip Flop
library ieee;use ieee.std_logic_1164.all;entity bejoy_rsff isport(s,r,clk:in std_logic;q,q1,z:inout std_logic);end bejoy_rsff;architecture arc of bejoy_rsff isbeginprocess(clk)beginif clk='1' thenz<=s or ((not r) and q);q<=z after 5ns;q1<=not z after 5ns;end if;end process;end a...
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