VHDL code for Basic Gates

AND Gate

library ieee;

use ieee.std_logic_1164.all;

entity and_gate is

port (a,b : in std_logic ;

c : out std_logic);

end and_gate;

architecture arc of and_gate is

begin

c <= a and b; end arc;


OR Gate

library ieee;

use ieee.std_logic_1164.all;

entity or_gate is

port (a,b : in std_logic ;

c : out std_logic);

end or_gate;

architecture arc of or_gate is

begin

c <= a or b; end arc;



NOT Gate

library ieee;

use ieee.std_logic_1164.all;

entity not_gate is

port (a: in std_logic ;

b : out std_logic);

end not_gate;

architecture arc of not_gate is

begin

b <= not a; end arc;


NAND Gate

library ieee;

use ieee.std_logic_1164.all;

entity nand_gate is

port (a,b : in std_logic ;

c : out std_logic);

end nand_gate;

architecture arc of nand_gate is

begin

c <= a or b; end arc;


NOR Gate

library ieee;

use ieee.std_logic_1164.all;

entity nor_gate is

port (a,b : in std_logic ;

c : out std_logic);

end nor_gate;

architecture arc of nor_gate is

begin

c <= a nor b; end arc;


XOR Gate

library ieee;

use ieee.std_logic_1164.all;

entity xor_gate is

port (a,b : in std_logic ;

c : out std_logic);

end xor_gate;

architecture arc of xor_gate is

begin

c <= a xor b;

end arc;