VHDL code for Half Subtractor

library ieee;
use ieee.std_logic_1164.all;

entity bejoy_hs is
port (x,y,en : in bit ;
d,b : out bit; y1: inout bit);
end bejoy_hs;

architecture arc of bejoy_hs is
begin
process (en,y1)
begin
if en='1' then
d<= x xor y;
y1<= not (y);
b <= x and y1;
end if;
end process;
end arc;