library ieee;
use ieee.std_logic_1164.all;
entity bejoy_b2g is
port(b:in std_logic_vector(3 downto 0);
g:out std_logic_vector(3 downto 0));
end bejoy_b2g;
architecture a of bejoy_b2g is
begin
g(3)<=b(3);
g(2)<=b(3) xor b(2);
g(1)<=b(2) xor b(1);
g(0)<=b(1) xor b(0);
end a;
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Friday, April 6, 2012
VHDL code for 4 bit Binary to Gray code converter
Friday, April 06, 2012
Electronics, VHDL