library IEEE;use IEEE.std_logic_1164.all;entity bejoy_4x1 isport(s1,s2,d00,d01,d10,d11 : in std_logic;z_out : out std_logic);end bejoy_4x1;architecture arc of bejoy_4x1 iscomponent muxport(sx1,sx2,d0,d1 : in std_logic;z : out std_logic);end component;component or_2port(a,b : in std_logic;c : out std_logic);end component;signal intr1, intr2, intr3, intr4 : std_logic;beginmux1 : mux port map(s1,s2,d00,d01,intr1);mux2 : mux port map(not s1,s2, d10,d11,intr2);o1 : or_2 port map(intr1, intr2, z_out);end arc;library ieee;use ieee.std_logic_1164.all;entity...